The performance of many digital systems is limited by the interconnection bandwidth between chips, boards, and cabinets. As VLSI technology continues to scale, system bandwidth will become an even more significant bottleneck as the number of I/Os scales more slowly than the bandwidth demands of on-chip logic. Also, off-chip signaling rates have historically scaled more slowly than on-chip clock rates. Most digital systems today use full-swing unterminated signaling methods that are unsuited for data rates over 100 MHz on one meter wires. Even good current-mode signaling methods with matched terminations and carefully controlled line and connector impedance are limited to about 1 GHz by the frequency-dependent attenuation of copper lines. Without new approaches to high-speed signaling, bandwidth will stop scaling with technology when we reach these limits.
Fully digital receiver equalizers, using finite impulse response (FIR) filters, require high-resolution sampling ADCs that run at GHz speeds, which is a challenging task in present CMOS technologies.
On the other hand, fully analog continuous-time equalizers have the disadvantage that the active equalizers need very wide-bandwidth front-end receiver circuits that run at the same speed as the input data signal, and the passive techniques attenuate the received signal amplitude resulting in large signal to noise ratio. The low Ft of transistors in present CMOS technologies makes receiver equalizer design quite challenging at multi-Gbps rates.
Input equalizers, reported to date in CMOS technology, all operate at data rates below 1.5 Gbps. See, for example, P. J. Black and T. Meng, “A 1-Gbps, four-state, sliding block Viterbi decoder,” IEEE JSSC, vol. 32, no. 6, June 1994; and Kamran Iravani et al., “Clock and data recovery for 1.25 Gb/s Ethernet Transceiver in 0.35-mm CMOS,” IEEE Custom Integrated Circuits Conference, page 261, May 1998.